fix(riscv): add low order bits to faulting address #190
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Signed-off-by: Jose Martins <[email protected]>
danielRep
approved these changes
Oct 31, 2024
ninolomata
approved these changes
Nov 4, 2024
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This PR fixes an issue identified in #188 where the address for trapped byte and halfword accesses did not result in the correct trapped address because the two lower order bits were not retrieved from stval.